During the production and further processing of chips, chip stacks are generated in order to increase the component density of the components. Such chip stacks (3D packages) are to include only functional chips (good chips).
It is known to electrically measure the wafers first in order to be able to distinguish good chips from unusable bad chips and to sort out the bad chips subsequently. For this purpose, after separation and thin grinding the chips are put on a carrier foil, the good chips are picked up, whereas the bad chips remain on the carrier foil. The drawback of this procedure is that for assembling the chips a serial process is used which is very time-consuming. The chip contacting devices (diebonder) used for this process step—if they have an output suitable for production—do not have the positioning accuracy of the chips necessary for the subsequent throughplating. On the other hand, chip contacting devices having a sufficient positioning accuracy do not achieve the output required for a production. Consequently, it is not possible in a satisfying way to pick up the individual good chips and stack them during running production.
Another known procedure is to generate chip stacks first by assembling the wafers on one another. In a subsequent step, those chip stacks are sorted out which contain defect chips (bad chips). A drawback of this procedure is that although the yield with regard to the wafers used is good, the number of faultless chip stacks is accordingly low.
Another known procedure is to unmatch the wafers first and to replace bad chips by good chips. In a further work step, the chips are then assembled on pre-existing chip stacks. The drawback of this procedure is that during unmatching the position of the chips on the carrier foil changes. This results in high position tolerances during the subsequent assembly of the chips. The chip stacks thus may not have the positioning accuracy necessary for a subsequent throughplating.